The government of the United States may have certain limited rights in the present invention. The present invention is a continuation-in-part of the following prior applications by the present applicant:                (1) an application titled “Magnetic Spin Transistor, Logic Gate & Method of Operation,” (Ser. No. 08/425,884, filed Apr. 21, 1995);        (2) an application titled “Magnetic Spin Transistor Hybrid Circuit Element,” (Ser. No. 08/493,815, issued Oct. 15, 1996 as U.S. Pat. No. 5,565,695);        (3) an application titled “Magnetic Spin Injected Field Effect Transistor and Method of Operation,” (Ser. No. 08/643,804 filed May 6, 1996);        (4) an application titled “Hybrid Hall Effect Device and Method of Operation,” (Ser. No. 08/643,805, filed May 6, 1996)        
The above materials are expressly incorporated by reference herein.
Hybrid Hall Effect devices are described in my earlier application (4) above. The present invention is directed to specific embodiments of such devices, as well as preferred arrangements of the same which result in improved memory elements and performance of memory arrays.
By modifying a classic Hall plate, and in particular by coupling it to a ferromagnetic material, novel hybrid devices can be created that are useful for applications in high density nonvolatile memory and logic gate environments. A schematic figure that can be used to represent the novel Hybrid Hall Effect Device 10 is illustrated in FIG. 1. A standard representation for a classic four-terminal Hall plate 12 is a cross centered in a square. Two opposing terminals are used for current bias (or voltage bias), for example terminals 14 and 16, and the other two terminals 18 and 20 are used for sensing a bipolar Hall voltage.
One embodiment of the hybrid Hall Effect device described in my earlier application (4) incorporates a ferromagnetic film F 22 fabricated to be electrically isolated from the Hall plate but covering a portion of the area of the Hall plate such that an edge 26 of the film is over a central region of the plate. Local, fringe magnetic fields from the edge of the ferromagnetic film are perpendicular to the plane of the plate, may point “up” or “down” depending on the orientation of the magnetization in F, and have an average value Bav in the active region of the device. For constant bias current the sensed Hall voltage has opposite polarity when the fringe fields are “up” compared with when they are “down.” The magnetization ^M 24 of F is typically in the plane of F and lies along an axis parallel with that of the bias current. Other orientations can be used however, such as magnetizations that are perpendicular to the plane instead. The magnetization can be configured to have two stable states along this axis, with the two states corresponding to “up” or “down” fringe fields near the edge of F, positive or negative Hall voltage, and thus representing a binary bit of information “1” or “0”. The magnetization state can be set (written) to be positive or negative by using the magnetic field associated with a positive or negative current pulse transmitted down an integrated write wire that is contiguous with F, discussed in detail in application (4) above, as well as below. It follows that such a device can be used as the nonvolatile storage element in an array of elements comprising a nonvolatile random access memory (NRAM). FIG. 1 depicts the first embodiment of the Hybrid Hall Effect device, generally referred to hereafter as a “modified hall plate.” Again, while application (4) describes one preferred physical embodiment of the modified hall plate, it will be understood by those skilled in the art that a variety of layer materials, layer structures and layer arrangements are possible.
My earlier application (4) described various arrangements of the type of hybrid Hall Effect devices described above which could be used as a memory array. In particular, a linear row of elements can be constructed with such devices, so that the positive current bias terminal of one element (e.g. terminal 14 in FIG. 1) is connected in series with the negative current bias terminal of another (e.g. terminal 16). In this way, a number ni of elements is combined in one row and biased by a single current (or voltage) supply source, IB or VB. Each element of that row can then be sensed by a unique sense amplifier devoted to that element. Alternatively, a single amplifier can be used for all elements in the row if a selection and isolation device is used to isolate each element from all of the other elements. A field effect transistor (FET) used in this manner can be referred to as a “select transistor.”
While the above memory array arrangement is satisfactory for many environments, other applications may experience undesirable problems when a number nj of rows are fabricated together to form an array of this type. In particular, because the hybrid Hall Effect memory cells are not isolated from each other, Hall voltages generated at one cell can dissipate through common connections to neighbor cells and the signal level, as well as the signal to noise ratio (SNR) of the readout voltage for every cell can be degraded. There is a need, therefore, for hybrid Hall Effect memory cell embodiments and arrangements which eliminate and/or reduce such performance problems.